In the field of testing digital electronic circuits, signature analysis has proved to be a successful method for determining the correct operation of the device under test (DUT). The basic technique of signature analysis is to reduce a stream of measured digital values associated with inputs to or outputs from the pins of the DUT to a simple unique signature. Hardware implementations of signature analyzers share several common features. There is commonly a shift register, feedback summing circuits, and a clock circuit. A signature is derived by summing, at each clock cycle, the just measured response with predefined bits from the shift register. Then the summation is shifted into one end of the shift register while dropping the bit on the other end of the shift register. These two steps may be repeated any number of clock cycles, thereby substantially reducing the data necessary to represent long streams of patterns.
Although this process reduces test time and cost, many electronic circuits cannot take advantage of this method of reducing test data. A major problem arises when the clock for the signature analyzer occurs when the measured response of the DUT is at an indeterminate value. This indeterminate value may result from:
1) a bidirectional bus in the high impedance state, or PA1 2) a latch that has not been reset or initialized, or PA1 3) a race or other unstable condition, or PA1 4) a time when fast circuits may correctly result in one value and slow circuits may result in another value. PA1 1) a temporary AC line variation due to a lighting storm, power station fluctuations, load surges, etc., PA1 2) an intermittent connection of a signal pin that changes continuity due to wind, being bumped, thermal expansion/contraction, etc., or PA1 3) a modeled device which does not reset to the identical state each and every iteration.
Each indeterminate value that is clocked into the summing circuit doubles the number of good signatures possible and halves the probability of generating unique signatures that will identify failures. This exponential growth in data and exponential drop in accuracy rapidly negates the benefits of signature analysis.
References to methods attempting to circumvent this problem for special cases are found in the prior art, but none describes a general method. For example, one technique synchronizes the signature clock with the DUT clock, as taught by U.S. Pat. No. 4,534,030. Articles in the IBM Technical Disclosure Bulletin, Oct. 1984 at pages 2749-2750 and Dec. 1984 at pages 3845-3847, have suggested complex methods that synchronize and degate the signature clock based on the specific DUT signals.
Less successfully, signature analysis has been used to diagnose failing electronic circuit assemblies. Signature analysis has not, heretofore, been used in the field of physical modeling.
Physical modeling is the field of computer simulation of electronic circuits wherein, in addition to the computer simulation of a substantial portion of an entire electronic circuit, actual hardware circuits and simulator interface programs, in addition to the traditional software behavior models, are used in the simulation process to represent another portion of the entire electronic circuit.
In the field of physical modeling, U.S. Pat. No. 4,590,581 describes an iterative technique in which the accumulated simulation patterns are reapplied to the physical model. Each new pattern is incrementally added to the set of previous patterns and then reapplied to the physical model in its entirety. Every iteration has to perform identically for their common set of patterns or erroneous computer simulation results will occur. Depending on the purpose of the computer simulation, the erroneous results could result in incorrect test data, logic design verification, or microcode verification results. A partial list of potential reasons why one iteration may deviate from previous iterations is as follows:
Current physical modeling systems ignore these potential problems, and leave the user to debug the erroneous results. Typically, the user will rerun the simulation and the problem will disappear. While the potential for such integrity problems may be relatively low, as the use of physical modeling has become more prevalent and simulation run times have increased, this problem has become unacceptable. It would, therefore, be of great benefit in the field of testing and physical modeling to generate output pin signatures having unquestionable integrity, and to use such signatures to add accuracy to the entire electronic hardware simulation process.